A vertical device architecture having ∼40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V DD<60;0.6V, while MOSFET is superior for V DD>0.6V. To further improve MOSFET performance, I ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C ov and C g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.