Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

H. Liu, D. K. Mohata, A. Nidhi, V. Saripalli, V. Narayanan, S. Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Scopus citations

Abstract

A vertical device architecture having ∼40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V DD<60;0.6V, while MOSFET is superior for V DD>0.6V. To further improve MOSFET performance, I ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C ov and C g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.

Original languageEnglish (US)
Title of host publication70th Device Research Conference, DRC 2012 - Conference Digest
Pages233-234
Number of pages2
DOIs
StatePublished - Oct 5 2012
Event70th Device Research Conference, DRC 2012 - University Park, PA, United States
Duration: Jun 18 2012Jun 20 2012

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Other

Other70th Device Research Conference, DRC 2012
CountryUnited States
CityUniversity Park, PA
Period6/18/126/20/12

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Liu, H., Mohata, D. K., Nidhi, A., Saripalli, V., Narayanan, V., & Datta, S. (2012). Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications. In 70th Device Research Conference, DRC 2012 - Conference Digest (pp. 233-234). [6256990] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2012.6256990