Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.

Original languageEnglish (US)
Title of host publicationProceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PublisherIEEE Computer Society
Pages565-570
Number of pages6
ISBN (Electronic)9781479975815
DOIs
StatePublished - Apr 13 2015
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: Mar 2 2015Mar 4 2015

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2015-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period3/2/153/4/15

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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