Abstract
Owing to the advantages of low standby power and high scalability, ReRAM technology is considered as a promising replacement for conventional DRAM in future manycore systems. In order to make ReRAM highly scalable, the memory array has to have a crossbar array structure, which needs a specific access mechanism for activating a row of memory when reading/writing a data block from/to it. This type of memory access would cause Sneak Current that would lead to voltage drop on the memory cells of the activated row, i.e., the cells which are far from the write drivers experience more voltage drop compared to those close to them. This results in a nonuniform access latency for the cells of the same row. To address this problem, we propose and evaluate a scheme that exploits the non-uniformity of write access pattern of the workloads. More specifically, based on our extensive characterization of write patterns to the cache lines and memory pages of 20 CPU workloads, we recognized that (i) on each main memory access, just a few cache lines of the activated row need to be updated on a write-back, and more importantly, there is a temporal and spatial locality of the writes to the cache lines; and (ii) all pages of the memory footprint of an application do not see the same write counts during the execution of the workload. Motivated by these characteristics, we then evaluate different intra-page memory block permutations in order to improve the performance of a crossbar ReRAM-based main memory. Our results collectively show that, by applying some types of intra-page memory block permutation, the access latency to a ReRAM-based main memory can be reduced up to 50% when running the SPEC CPU2006 workloads.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 167-176 |
| Number of pages | 10 |
| ISBN (Electronic) | 9781538612323 |
| DOIs | |
| State | Published - Dec 5 2017 |
| Event | 2017 IEEE International Symposium on Workload Characterization, IISWC 2017 - Seattle, United States Duration: Oct 1 2017 → Oct 3 2017 |
Publication series
| Name | Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017 |
|---|---|
| Volume | 2017-January |
Other
| Other | 2017 IEEE International Symposium on Workload Characterization, IISWC 2017 |
|---|---|
| Country | United States |
| City | Seattle |
| Period | 10/1/17 → 10/3/17 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Information Systems and Management
Cite this
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Exploring the impact of memory block permutation on performance of a crossbar ReRAM main memory. / Ramezani, Morteza; Elyasi, Nima; Arjomand, Mohammad; Kandemir, Mahmut; Sivasubramaniam, Anand.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 167-176 (Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017; Vol. 2017-January).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Exploring the impact of memory block permutation on performance of a crossbar ReRAM main memory
AU - Ramezani, Morteza
AU - Elyasi, Nima
AU - Arjomand, Mohammad
AU - Kandemir, Mahmut
AU - Sivasubramaniam, Anand
PY - 2017/12/5
Y1 - 2017/12/5
N2 - Owing to the advantages of low standby power and high scalability, ReRAM technology is considered as a promising replacement for conventional DRAM in future manycore systems. In order to make ReRAM highly scalable, the memory array has to have a crossbar array structure, which needs a specific access mechanism for activating a row of memory when reading/writing a data block from/to it. This type of memory access would cause Sneak Current that would lead to voltage drop on the memory cells of the activated row, i.e., the cells which are far from the write drivers experience more voltage drop compared to those close to them. This results in a nonuniform access latency for the cells of the same row. To address this problem, we propose and evaluate a scheme that exploits the non-uniformity of write access pattern of the workloads. More specifically, based on our extensive characterization of write patterns to the cache lines and memory pages of 20 CPU workloads, we recognized that (i) on each main memory access, just a few cache lines of the activated row need to be updated on a write-back, and more importantly, there is a temporal and spatial locality of the writes to the cache lines; and (ii) all pages of the memory footprint of an application do not see the same write counts during the execution of the workload. Motivated by these characteristics, we then evaluate different intra-page memory block permutations in order to improve the performance of a crossbar ReRAM-based main memory. Our results collectively show that, by applying some types of intra-page memory block permutation, the access latency to a ReRAM-based main memory can be reduced up to 50% when running the SPEC CPU2006 workloads.
AB - Owing to the advantages of low standby power and high scalability, ReRAM technology is considered as a promising replacement for conventional DRAM in future manycore systems. In order to make ReRAM highly scalable, the memory array has to have a crossbar array structure, which needs a specific access mechanism for activating a row of memory when reading/writing a data block from/to it. This type of memory access would cause Sneak Current that would lead to voltage drop on the memory cells of the activated row, i.e., the cells which are far from the write drivers experience more voltage drop compared to those close to them. This results in a nonuniform access latency for the cells of the same row. To address this problem, we propose and evaluate a scheme that exploits the non-uniformity of write access pattern of the workloads. More specifically, based on our extensive characterization of write patterns to the cache lines and memory pages of 20 CPU workloads, we recognized that (i) on each main memory access, just a few cache lines of the activated row need to be updated on a write-back, and more importantly, there is a temporal and spatial locality of the writes to the cache lines; and (ii) all pages of the memory footprint of an application do not see the same write counts during the execution of the workload. Motivated by these characteristics, we then evaluate different intra-page memory block permutations in order to improve the performance of a crossbar ReRAM-based main memory. Our results collectively show that, by applying some types of intra-page memory block permutation, the access latency to a ReRAM-based main memory can be reduced up to 50% when running the SPEC CPU2006 workloads.
UR - http://www.scopus.com/inward/record.url?scp=85043513201&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85043513201&partnerID=8YFLogxK
U2 - 10.1109/IISWC.2017.8167774
DO - 10.1109/IISWC.2017.8167774
M3 - Conference contribution
AN - SCOPUS:85043513201
T3 - Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017
SP - 167
EP - 176
BT - Proceedings of the 2017 IEEE International Symposium on Workload Characterization, IISWC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -