Extended addressing mode for low power

Atul Kalambur, Mary Jane Irwin

Research output: Contribution to conferencePaper

Abstract

This paper demonstrates the feasibility of a register-memory addressing mode in microprocessors targeted for low power applications. Using a high level power profiling tool that performs software energy evaluation, the major sources of power dissipation in a typical RISC processor are identified. It is shown that the addition of a register-memory addressing mode can target these `hot-spots' and provide power savings. Two different implementation options are considered and the power-performance trade-offs are evaluated. The reduction in performance is cushioned by the reduced instruction count, and it is anticipated that the overall impact on the total execution time of programs will be acceptable in low power application domains.

Original languageEnglish (US)
Pages208-213
Number of pages6
DOIs
StatePublished - Jan 1 1997
EventProceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: Aug 18 1997Aug 20 1997

Other

OtherProceedings of the 1997 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period8/18/978/20/97

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Kalambur, A., & Irwin, M. J. (1997). Extended addressing mode for low power. 208-213. Paper presented at Proceedings of the 1997 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, . https://doi.org/10.1145/263272.263336