Fast, bit-accurate simulation of truncated-matrix multipliers and squarers

E. George Walters, Michael J. Schulte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Truncated-matrix multipliers and squarers offer significant reductions in area, power, and delay, at the expense of increased computational error. These trade-offs make them an attractive choice for many signal processing systems. However, extensive bit-accurate simulation is often necessary to explore the design space effectively and chose the best parameters when using them in systems. This paper presents an algorithm for fast, bit-accurate simulation of truncated-matrix multipliers and squarers in software. The algorithm is applicable to most correction methods published to date, is simple to implement, and it facilitates research into system-level use of truncated-matrix units.

Original languageEnglish (US)
Title of host publicationConference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
Pages1139-1143
Number of pages5
DOIs
StatePublished - Dec 1 2010
Event44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 - Pacific Grove, CA, United States
Duration: Nov 7 2010Nov 10 2010

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
CountryUnited States
CityPacific Grove, CA
Period11/7/1011/10/10

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Signal processing

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

Cite this

Walters, E. G., & Schulte, M. J. (2010). Fast, bit-accurate simulation of truncated-matrix multipliers and squarers. In Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 (pp. 1139-1143). [5757582] (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/ACSSC.2010.5757582
Walters, E. George ; Schulte, Michael J. / Fast, bit-accurate simulation of truncated-matrix multipliers and squarers. Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010. 2010. pp. 1139-1143 (Conference Record - Asilomar Conference on Signals, Systems and Computers).
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Walters, EG & Schulte, MJ 2010, Fast, bit-accurate simulation of truncated-matrix multipliers and squarers. in Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010., 5757582, Conference Record - Asilomar Conference on Signals, Systems and Computers, pp. 1139-1143, 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010, Pacific Grove, CA, United States, 11/7/10. https://doi.org/10.1109/ACSSC.2010.5757582

Fast, bit-accurate simulation of truncated-matrix multipliers and squarers. / Walters, E. George; Schulte, Michael J.

Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010. 2010. p. 1139-1143 5757582 (Conference Record - Asilomar Conference on Signals, Systems and Computers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Walters EG, Schulte MJ. Fast, bit-accurate simulation of truncated-matrix multipliers and squarers. In Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010. 2010. p. 1139-1143. 5757582. (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/ACSSC.2010.5757582