Fast compact addition architecture for low power microprocessors and DSP chips

Eric S. Gayles, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journalConference article

Abstract

An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits.

Original languageEnglish (US)
Pages (from-to)41-44
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 1996
EventProceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA
Duration: Sep 23 1996Sep 27 1996

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Adders
Digital signal processors
Microprocessor chips
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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Fast compact addition architecture for low power microprocessors and DSP chips. / Gayles, Eric S.; Owens, Robert M.; Irwin, Mary Jane.

In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 01.01.1996, p. 41-44.

Research output: Contribution to journalConference article

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