Fast Methods for Switch-Level Verification of MOS Circuits

Douglas S. Reeves, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

Original languageEnglish (US)
Pages (from-to)766-779
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume6
Issue number5
DOIs
StatePublished - Jan 1 1987

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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