The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch graph are developed. Secondly, static analysis of the switch graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is utilized safely to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.
|Original language||English (US)|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Sep 1 1986|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering