Fault tolerant signal processing for masking translent errors in VLSI signal processors

William Kenneth Jenkins, C. Radhakrishnan, S. Pal

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

This paper proposes fault tolerant signal processing strategies for achieving reliable performance in VLSI signal processors that are prone to transient errors due to increasingly smaller feature dimensions and supply voltages. The proposed methods are based on residue number system (RNS) coding, involving either hardware redundancy or multiple execution redundancy (MER) strategies designed to identify and overcome transient errors. RNS techniques provide powerful low-redundancy fault tolerance properties that must be introduced at VLSI design levels, whereas MER strategies generally require higher degrees of redundancy that can be introduced at software programming levels.

Original languageEnglish (US)
Article number4253202
Pages (from-to)2570-2573
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Sep 27 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: May 27 2007May 30 2007

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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