Folded cascode CMOS mixer design and optimization in 70 nm technology

Eugene Shevchuk, Kyusun Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

A 2.4 GHz CMOS RF mixer is designed using 70 nm technology in order to maximize potential efficiency and minimize power consumption. Running the circuit at low voltages brings in a concern for headroom, as it becomes more difficult to correctly bias stacks of transistors like those found in a standard Gilbert cell. In order to reliably run the circuit at 0.7 V, the Gilbert cell design is revised using the established concept of folded cascode. The revisions also serve to improve secondary features of the mixer such as linearity and input transistor transconductance. The simulated circuit exhibits a 1.4dB conversion loss, -11.5 dBm LO power, -0.5 dBm at the IP3 and 0.7 mW consumed in the mixer itself.

Original languageEnglish (US)
Title of host publication2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages943-946
Number of pages4
DOIs
StatePublished - Dec 1 2005
Event2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States
Duration: Aug 7 2005Aug 10 2005

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2005
ISSN (Print)1548-3746

Other

Other2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
CountryUnited States
CityCincinnati, OH
Period8/7/058/10/05

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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