Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin, Mahmut Kandemir

Research output: Contribution to conferencePaper

15 Citations (Scopus)

Abstract

Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.

Original languageEnglish (US)
Pages248-253
Number of pages6
StatePublished - Jan 1 2001
Event14th International Conference on VLSI Design (VLSI DESIGN 2001) - Bangalore, India
Duration: Jan 3 2001Jan 7 2001

Other

Other14th International Conference on VLSI Design (VLSI DESIGN 2001)
CountryIndia
CityBangalore
Period1/3/011/7/01

Fingerprint

Electric power distribution
Clocks
Energy dissipation
Mobile devices
Electron energy levels
Microprocessor chips
Precipitates
Electric power utilization
Simulators

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Duarte, D., Narayanan, V., Irwin, M. J., & Kandemir, M. (2001). Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks. 248-253. Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.
Duarte, D. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Kandemir, Mahmut. / Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks. Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.6 p.
@conference{67b2d76e99f74b7dbb94645eafbbfbe0,
title = "Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks",
abstract = "Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.",
author = "D. Duarte and Vijaykrishnan Narayanan and Irwin, {Mary Jane} and Mahmut Kandemir",
year = "2001",
month = "1",
day = "1",
language = "English (US)",
pages = "248--253",
note = "14th International Conference on VLSI Design (VLSI DESIGN 2001) ; Conference date: 03-01-2001 Through 07-01-2001",

}

Duarte, D, Narayanan, V, Irwin, MJ & Kandemir, M 2001, 'Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks' Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India, 1/3/01 - 1/7/01, pp. 248-253.

Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks. / Duarte, D.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Kandemir, Mahmut.

2001. 248-253 Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.

Research output: Contribution to conferencePaper

TY - CONF

T1 - Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

AU - Duarte, D.

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

AU - Kandemir, Mahmut

PY - 2001/1/1

Y1 - 2001/1/1

N2 - Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.

AB - Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.

UR - http://www.scopus.com/inward/record.url?scp=0035007816&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035007816&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0035007816

SP - 248

EP - 253

ER -

Duarte D, Narayanan V, Irwin MJ, Kandemir M. Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks. 2001. Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.