Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin, Mahmut Kandemir

Research output: Contribution to conferencePaper

15 Scopus citations

Abstract

Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.

Original languageEnglish (US)
Pages248-253
Number of pages6
StatePublished - Jan 1 2001
Event14th International Conference on VLSI Design (VLSI DESIGN 2001) - Bangalore, India
Duration: Jan 3 2001Jan 7 2001

Other

Other14th International Conference on VLSI Design (VLSI DESIGN 2001)
CountryIndia
CityBangalore
Period1/3/011/7/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Duarte, D., Narayanan, V., Irwin, M. J., & Kandemir, M. (2001). Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks. 248-253. Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.