FPGA-accelerated simulation of truncated-matrix multipliers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Truncated-matrix multipliers offer significant reductions in area, power and delay, at the expense of increased computational error. Extensive bit-accurate simulation is often necessary to evaluate the trade-offs and choose the best parameters for a particular application. This paper presents a method for simulating truncated-matrix multipliers using a field-programmable gate array (FPGA). The method is applicable to most error correction methods published to date, and is simple to implement. It enables real-time simulation in actual applications, exhaustive simulation of large design spaces, and Monte Carlo simulation with more trials than other simulation options. When implemented in a Virtex-5 FPGA, the simulation runs at the same speed as a standard round-to-nearest multiplier, performing more than 229 simulations per second per embedded multiplier.

Original languageEnglish (US)
Title of host publicationConference Record of the 46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
Pages993-997
Number of pages5
DOIs
StatePublished - Dec 1 2012
Event46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012 - Pacific Grove, CA, United States
Duration: Nov 4 2012Nov 7 2012

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other46th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2012
CountryUnited States
CityPacific Grove, CA
Period11/4/1211/7/12

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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