FPGA-based test bed for design and evaluation of low-power FIR-filter hardware accelerators

Eugene George Walters, III, Joshua J. Arner, Noah D. Rojahn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Finite impulse response (FIR) filters are often used for processing audio, communication and other signals. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a test bed for low-power FIR-filter hardware accelerators that use truncated-matrix multipliers. It accepts analog input signals, filters them in real-time using an inexpensive field-programmable gate array (FPGA) development board, and produces analog outputs. The input is simultaneously processed using truncated-matrix multipliers and standard multipliers for comparison. Parameters such as filter coefficients, the number of unformed columns and the error correction method can be changed on the fly. The test bed enables real-time testing at the systems-integration level using real analog inputs and outputs.

Original languageEnglish (US)
Title of host publication2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012
DOIs
StatePublished - Sep 26 2012
Event2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012 - Harrisburg, PA, United States
Duration: Jun 4 2012Jun 6 2012

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

Other2012 IEEE 16th International Symposium on Consumer Electronics, ISCE 2012
CountryUnited States
CityHarrisburg, PA
Period6/4/126/6/12

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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