In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.
|Original language||English (US)|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 1 1992|
|Event||14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, United States|
Duration: May 3 1992 → May 6 1992
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering