Fully parallel digital implementation of connectionist associative memory

Kyusun Choi, William S. Adams

Research output: Contribution to journalConference article

Abstract

In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.

Original languageEnglish (US)
Article number5727297
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - Dec 1 1992

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Neurons
Neural networks
Data storage equipment
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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title = "Fully parallel digital implementation of connectionist associative memory",
abstract = "In this paper, the authors present a binary weight pattern associator circuit, a fully parallel digital connectionist associative memory, with 127 neurons and 16,129 interconnections which can be implemented on a 1cm 2 CMOS VLSI chip capable of operating at 484 billion interconnections per second. The performance estimate of the chip is significantly improved over other neural network implementations.",
author = "Kyusun Choi and Adams, {William S.}",
year = "1992",
month = "12",
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Fully parallel digital implementation of connectionist associative memory. / Choi, Kyusun; Adams, William S.

In: Proceedings of the Custom Integrated Circuits Conference, 01.12.1992.

Research output: Contribution to journalConference article

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