Fully self-aligned tri-layer a-Si: H TFT with ultra-thin active layer

D. B. Thomasson, Thomas Nelson Jackson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Parasitic capacitance from gate-to-source contact overlap is a major factor limiting the performance of hydrogenated amorphous silicon thin-film transistors for active matrix liquid crystal displays. A self-aligned thin-film transistors is proposed to minimize this parasitic capacitance. Self-alignment is typically achieved with a single backside exposure photolithography step, using the bottom gate to define the channel region. A simple processing method is described for fully self-aligned tri-layer thin-film transistor (TFT) with deposited n+ contacts. In addition, these fully self-aligned TFTs have an ultra-thin a-Si:H layer that results in improved performance.

Original languageEnglish (US)
Title of host publicationAnnual Device Research Conference Digest
PublisherIEEE
Pages50-51
Number of pages2
Publication statusPublished - 1997
EventProceedings of the 1997 55th Annual Device Research Conference - Fort Collins, CO, USA
Duration: Jun 23 1997Jun 25 1997

Other

OtherProceedings of the 1997 55th Annual Device Research Conference
CityFort Collins, CO, USA
Period6/23/976/25/97

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Thomasson, D. B., & Jackson, T. N. (1997). Fully self-aligned tri-layer a-Si: H TFT with ultra-thin active layer. In Annual Device Research Conference Digest (pp. 50-51). IEEE.