FUNCTIONAL VERIFICATION OF DIGITAL MOS CIRCUITS.

Douglas S. Reeves, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A major goal of the Snap CAD system for automatically generating signal-processing circuits is to prove that the designs are functionally correct. The function of a MOS circuit is extracted using techniques due to R. Bryant (1985). This functional characterization is compared to the high-level description of the circuit to determine correctness. Important aspects of the verifier are: 1) paths in the switch graph are compiled statically; 2) cells in a hierarchical design are functionally meaningful and may be abstracted for use in verifying the entire design; and 3) optimized algorithms make interactive verification feasible. Experimental results are presented.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages496-499
Number of pages4
ISBN (Print)0818607440
StatePublished - Dec 1 1986

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Reeves, D. S., & Irwin, M. J. (1986). FUNCTIONAL VERIFICATION OF DIGITAL MOS CIRCUITS. In Unknown Host Publication Title (pp. 496-499). IEEE.