Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Sang Phill Park; Sumeet Gupta; Niladri Mojumder; Anand Raghunathan; Kaushik Roy

doi:10.1145/2228360.2228447

Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Sang Phill Park, Sumeet Gupta, Niladri Mojumder, Anand Raghunathan, Kaushik Roy

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

68 Scopus citations

Abstract

Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose micro-architectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.

Original language	English (US)
Title of host publication	Proceedings of the 49th Annual Design Automation Conference, DAC '12
Pages	492-497
Number of pages	6
DOIs	https://doi.org/10.1145/2228360.2228447
State	Published - Jul 11 2012
Event	49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States Duration: Jun 3 2012 → Jun 7 2012

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	49th Annual Design Automation Conference, DAC '12
Country	United States
City	San Francisco, CA
Period	6/3/12 → 6/7/12

All Science Journal Classification (ASJC) codes

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1145/2228360.2228447

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title = "Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture",

abstract = "Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose micro-architectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.",

author = "Park, {Sang Phill} and Sumeet Gupta and Niladri Mojumder and Anand Raghunathan and Kaushik Roy",

year = "2012",

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language = "English (US)",

isbn = "9781450311991",

series = "Proceedings - Design Automation Conference",

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note = "49th Annual Design Automation Conference, DAC '12 ; Conference date: 03-06-2012 Through 07-06-2012",

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Park, SP, Gupta, S, Mojumder, N, Raghunathan, A & Roy, K 2012, Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture. in Proceedings of the 49th Annual Design Automation Conference, DAC '12. Proceedings - Design Automation Conference, pp. 492-497, 49th Annual Design Automation Conference, DAC '12, San Francisco, CA, United States, 6/3/12. https://doi.org/10.1145/2228360.2228447

Future cache design using STT MRAMs for improved energy efficiency : Devices, circuits and architecture. / Park, Sang Phill; Gupta, Sumeet; Mojumder, Niladri; Raghunathan, Anand; Roy, Kaushik.

Proceedings of the 49th Annual Design Automation Conference, DAC '12. 2012. p. 492-497 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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