Geometric tiling for reducing power consumption in structured matrix operations

G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, Mahmut Kandemir, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric riling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.

Original languageEnglish (US)
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
Pages113-114
Number of pages2
DOIs
StatePublished - Dec 1 2007
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: Sep 24 2006Sep 27 2006

Other

Other2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period9/24/069/27/06

Fingerprint

Electric power utilization
Tile
Geometry

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chen, G., Xue, L., Kim, J., Sobti, K., Deng, L., Sun, X., ... Narayanan, V. (2007). Geometric tiling for reducing power consumption in structured matrix operations. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 113-114). [4063030] https://doi.org/10.1109/SOCC.2006.283861
Chen, G. ; Xue, L. ; Kim, J. ; Sobti, K. ; Deng, L. ; Sun, X. ; Pitsianis, N. ; Chakrabarti, C. ; Kandemir, Mahmut ; Narayanan, Vijaykrishnan. / Geometric tiling for reducing power consumption in structured matrix operations. 2006 IEEE International Systems-on-Chip Conference, SOC. 2007. pp. 113-114
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Chen, G, Xue, L, Kim, J, Sobti, K, Deng, L, Sun, X, Pitsianis, N, Chakrabarti, C, Kandemir, M & Narayanan, V 2007, Geometric tiling for reducing power consumption in structured matrix operations. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063030, pp. 113-114, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283861

Geometric tiling for reducing power consumption in structured matrix operations. / Chen, G.; Xue, L.; Kim, J.; Sobti, K.; Deng, L.; Sun, X.; Pitsianis, N.; Chakrabarti, C.; Kandemir, Mahmut; Narayanan, Vijaykrishnan.

2006 IEEE International Systems-on-Chip Conference, SOC. 2007. p. 113-114 4063030.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chen G, Xue L, Kim J, Sobti K, Deng L, Sun X et al. Geometric tiling for reducing power consumption in structured matrix operations. In 2006 IEEE International Systems-on-Chip Conference, SOC. 2007. p. 113-114. 4063030 https://doi.org/10.1109/SOCC.2006.283861