In this article, we propose a hardware architecture for our fast Intra mode and direction prediction algorithm to accelerate the MPEG-2 to H.264/AVC transcoding devices. In order to eliminate the redundant operations in the transcoder, our implemented algorithm uses the DCT coefficients from the MPEG-2 decoder to predict the Intra mode and reconstruction direction for the H.264/AVC encoder. In addition, the Intra prediction process in the H.264/AVC part of the transcoder has been dramatically accelerated by using our full-search elimination technique. The empirical results show 92% reduction in the transcoding time while reducing the PSNR for less than 3.5%. The proposed architecture has achieved an operating frequency of 323MHz at a power consumption of 112 mW when implemented on Virtex-5 FPGA Development Board.