Harnessing ferroelectrics for non-volatile memories and logic

Sumeet Kumar Gupta, Danni Wang, Sumitha George, Ahmedullah Aziz, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Ferroelectrics (FE) have been the materials of interest for non-volatile memories for many decades due to their hysteretic charge-voltage behavior. However, recently, the possibilities of integrating an FE in the gate stack of a transistor (forming a ferroelectric transistor or FEFET) have opened new avenues for computation and storage. The FEFETs not only enhance the design of non-volatile memories, but also lead to the unique possibilities of introducing non-volatility in close proximity with the compute elements. In this paper, we comparatively analyze several device and circuit aspects of FEFETs and FE capacitors from the perspective of designing non-volatile memory and logic. We discuss the effect of integrating an FE in a transistor structure on the remnant polarization and coercive voltage and show the importance of FE thickness optimization to design a non-volatile transistor. We also present circuit design possibilities with non-volatile FEFETs. First, the design of memories with separate read-write paths is discussed. We show that compared to FE capacitor based memories, FEFETs achieve enormous distinguishability and near read disturb free operation albeit with 2.5× higher cell area and 3.6× higher write energy at iso-write time. Second, we describe the opportunities that non-volatility combined with the three terminal architecture of FEFETs presents in the design of low power non-volatile flip-flops. We show that compared to FE capacitor based flip-flops, FEFET based design yields upto 50% lower energy and up to 40% lower delay for data back-up, along with 30% lower area.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages29-34
Number of pages6
ISBN (Electronic)9781509054046
DOIs
StatePublished - May 2 2017
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: Mar 14 2017Mar 15 2017

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period3/14/173/15/17

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Gupta, S. K., Wang, D., George, S., Aziz, A., Li, X., Datta, S., & Narayanan, V. (2017). Harnessing ferroelectrics for non-volatile memories and logic. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 29-34). [7918288] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918288