Hazard driven test generation for SMT processors

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages256-259
Number of pages4
ISBN (Print)9783981080186
DOIs
StatePublished - Jan 1 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: Mar 12 2012Mar 16 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
CountryGermany
CityDresden
Period3/12/123/16/12

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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