Hazard driven test generation for SMT processors

Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Pages256-259
Number of pages4
StatePublished - May 24 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: Mar 12 2012Mar 16 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
CountryGermany
CityDresden
Period3/12/123/16/12

Fingerprint

Hazards
Pipelines
Throughput

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Singh, P., Narayanan, V., & Landis, D. L. (2012). Hazard driven test generation for SMT processors. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 (pp. 256-259). [6176472] (Proceedings -Design, Automation and Test in Europe, DATE).
Singh, Padmaraj ; Narayanan, Vijaykrishnan ; Landis, David L. / Hazard driven test generation for SMT processors. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. pp. 256-259 (Proceedings -Design, Automation and Test in Europe, DATE).
@inproceedings{d65635c14de242fab1a8f3ef857fca56,
title = "Hazard driven test generation for SMT processors",
abstract = "Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.",
author = "Padmaraj Singh and Vijaykrishnan Narayanan and Landis, {David L.}",
year = "2012",
month = "5",
day = "24",
language = "English (US)",
isbn = "9783981080186",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
pages = "256--259",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012",

}

Singh, P, Narayanan, V & Landis, DL 2012, Hazard driven test generation for SMT processors. in Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012., 6176472, Proceedings -Design, Automation and Test in Europe, DATE, pp. 256-259, 15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012, Dresden, Germany, 3/12/12.

Hazard driven test generation for SMT processors. / Singh, Padmaraj; Narayanan, Vijaykrishnan; Landis, David L.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. p. 256-259 6176472 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Hazard driven test generation for SMT processors

AU - Singh, Padmaraj

AU - Narayanan, Vijaykrishnan

AU - Landis, David L.

PY - 2012/5/24

Y1 - 2012/5/24

N2 - Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.

AB - Multithreaded processors increase throughput by executing multiple independent programs on a single pipeline. Simultaneous Multithreaded (SMT) processors execute multiple threads simultaneously thus add a significant dimension to the design complexity. Dealing with this complexity calls for extended and innovative design verification efforts. This paper develops an analytic model based SMT random test generation technique. SMT analytic model parameters are applied to create random tests with high utilization and increased contention. To demonstrate the methodology, parameters extracted from the PPC ISA and sample processor configurations are simulated on the SMT analytic model. The methodology focuses on exploiting data/control and structural hazards to guide the random test generator to create effective SMT tests.

UR - http://www.scopus.com/inward/record.url?scp=84862090082&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862090082&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783981080186

T3 - Proceedings -Design, Automation and Test in Europe, DATE

SP - 256

EP - 259

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012

ER -

Singh P, Narayanan V, Landis DL. Hazard driven test generation for SMT processors. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012. 2012. p. 256-259. 6176472. (Proceedings -Design, Automation and Test in Europe, DATE).