HeTERO: Hybrid topology exploration for RF-based on-chip networks

Soumya Eachempati, Reetuparna Das, Vijaykrishnan Narayanan, Yuan Xie, Suman Datta, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Future microprocessors are predicted to consist of 10s to 100s of cores running several concurrent tasks. A scalable communication fabric is required to connect these components and thus, giving birth to networks on silicon, also known as Network-on-Chip (NoC). NoCs are being used as the de facto solution for integrating the multicore architectures, as opposed to point-topoint global wiring, shared buses, or monolithic crossbars, because of their scalability and predictable electrical properties.

Original languageEnglish (US)
Title of host publicationCommunication Architectures for Systems-on-Chip
PublisherCRC Press
Pages201-248
Number of pages48
ISBN (Electronic)9781439841716
ISBN (Print)9781138117945
StatePublished - Jan 1 2011

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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  • Cite this

    Eachempati, S., Das, R., Narayanan, V., Xie, Y., Datta, S., & Das, C. R. (2011). HeTERO: Hybrid topology exploration for RF-based on-chip networks. In Communication Architectures for Systems-on-Chip (pp. 201-248). CRC Press.