High performance array processor for video decoding

J. Lee, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, high performance array processor for signal processing algorithms with high computational complexities is implemented using 0.16 μm CMOS standard cell library. The proposed array processor consists of simple processing elements. The architectural benefits of highly regular, parallel, and pipelined processing elements simplify the design of complex signal processing systems and enable high throughput rate by massive parallel computations. We show the utility of the proposed architecture as a configurable core by mapping inverse discrete cosine transform (IDCT), motion compensation (MC), and inverse quantization (IQ) onto the proposed fabric. In addition, we propose a novel scheme that integrates the inverse quantization part of video decoding into the 2-D IDCT process simplifying computational logics. The results show that a high throughput rate to meet the real-time requirement is effectively achieved by exploiting the properties of both compressed video data statistics and the array processor architecture.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
EditorsA. Smailagic, N. Ranganathan
Pages28-33
Number of pages6
StatePublished - Oct 25 2005
EventIEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design - Tampa, FL, United States
Duration: May 11 2005May 12 2005

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Other

OtherIEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
CountryUnited States
CityTampa, FL
Period5/11/055/12/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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