High-performance low-energy STT MRAM based on balanced write scheme

Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

40 Scopus citations

Abstract

It is well known that high write time/energy in STT MRAM are aggravated by the asymmetry in write currents for '0'→'1' and '1'→'0' transitions. This asymmetry is primarily due to the source degeneration of the access transistor during write. In this work, we propose a design methodology which avoids the source degeneration of the access transistor, leading to balanced switching times for '0'→'1' and '1'→'0' transitions. This is achieved by using an additional (negative) bit-line voltage and reduced word-line voltage. The proposed method reduces write time (by ∼40%) and write energy (by 65%), enhances reliability of MTJ, and significantly improves tolerance to process variation. In the proposed scheme, source-line can be directly connected to ground signal leading to a compact cell layout.

Original languageEnglish (US)
Title of host publicationISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design
Pages9-14
Number of pages6
DOIs
StatePublished - Sep 4 2012
Event2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12 - Redondo Beach, CA, United States
Duration: Jul 30 2012Aug 1 2012

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2012 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'12
CountryUnited States
CityRedondo Beach, CA
Period7/30/128/1/12

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Lee, D., Gupta, S. K., & Roy, K. (2012). High-performance low-energy STT MRAM based on balanced write scheme. In ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design (pp. 9-14). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/2333660.2333665