High-performance transactions for persistent memories

Aasheesh Kolli, Steven Pelley, Ali Saidi, Peter M. Chen, Thomas F. Wenisch

Research output: Contribution to journalArticlepeer-review

24 Scopus citations

Abstract

Emerging non-volatile memory (NVRAM) technologies offer the durability of disk with the byte-addressability of DRAM. These devices will allow software to access persistent data structures directly in NVRAM using processor loads and stores, however, ensuring consistency of persistent data across power failures and crashes is difficult. Atomic, durable transactions are a widely used abstraction to enforce such consistency. Implementing transactions on NVRAM requires the ability to constrain the order of NVRAM writes, for example, to ensure that a transaction's log record is complete before it is marked committed. Since NVRAM write latencies are expected to be high, minimizing these ordering constraints is critical for achieving high performance. Recent work has proposed programming interfaces to express NVRAM write ordering constraints to hardware so that NVRAM writes may be coalesced and reordered while preserving necessary constraints. Unfortunately, a straightforward implementation of transactions under these interfaces imposes unnecessary constraints. We show how to remove these dependencies through a variety of techniques, notably, deferring commit until after locks are released. We present a comprehensive analysis contrasting two transaction designs across three NVRAM programming interfaces, demonstrating up to 2.5x speedup.

Original languageEnglish (US)
Pages (from-to)399-411
Number of pages13
JournalACM SIGPLAN Notices
Volume51
Issue number4
DOIs
StatePublished - Apr 2016

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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