High-speed, low-voltage complementary heterostructure FET circuit technology

R. A. Kiehl, J. Yates, L. F. Palmateer, S. L. Wright, D. J. Frank, Thomas Nelson Jackson, J. F. Degelormo, A. J. Fleischman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.

Original languageEnglish (US)
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
PublisherPubl by IEEE
Pages101-104
Number of pages4
ISBN (Print)078030196X
StatePublished - Jan 1 1992
Event13th Annual GaAs IC Symposium Technical Digest - Monterey, CA, USA
Duration: Oct 20 1991Oct 23 1991

Publication series

NameTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Other

Other13th Annual GaAs IC Symposium Technical Digest
CityMonterey, CA, USA
Period10/20/9110/23/91

Fingerprint

Field effect transistors
Heterojunctions
Networks (circuits)
Electric potential
Semiconductor quantum wells
Fabrication
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kiehl, R. A., Yates, J., Palmateer, L. F., Wright, S. L., Frank, D. J., Jackson, T. N., ... Fleischman, A. J. (1992). High-speed, low-voltage complementary heterostructure FET circuit technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 101-104). (Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)). Publ by IEEE.
Kiehl, R. A. ; Yates, J. ; Palmateer, L. F. ; Wright, S. L. ; Frank, D. J. ; Jackson, Thomas Nelson ; Degelormo, J. F. ; Fleischman, A. J. / High-speed, low-voltage complementary heterostructure FET circuit technology. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1992. pp. 101-104 (Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)).
@inproceedings{4123b376b8954f25b1be87e64501680a,
title = "High-speed, low-voltage complementary heterostructure FET circuit technology",
abstract = "A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.",
author = "Kiehl, {R. A.} and J. Yates and Palmateer, {L. F.} and Wright, {S. L.} and Frank, {D. J.} and Jackson, {Thomas Nelson} and Degelormo, {J. F.} and Fleischman, {A. J.}",
year = "1992",
month = "1",
day = "1",
language = "English (US)",
isbn = "078030196X",
series = "Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)",
publisher = "Publ by IEEE",
pages = "101--104",
booktitle = "Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)",

}

Kiehl, RA, Yates, J, Palmateer, LF, Wright, SL, Frank, DJ, Jackson, TN, Degelormo, JF & Fleischman, AJ 1992, High-speed, low-voltage complementary heterostructure FET circuit technology. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit), Publ by IEEE, pp. 101-104, 13th Annual GaAs IC Symposium Technical Digest, Monterey, CA, USA, 10/20/91.

High-speed, low-voltage complementary heterostructure FET circuit technology. / Kiehl, R. A.; Yates, J.; Palmateer, L. F.; Wright, S. L.; Frank, D. J.; Jackson, Thomas Nelson; Degelormo, J. F.; Fleischman, A. J.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE, 1992. p. 101-104 (Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - High-speed, low-voltage complementary heterostructure FET circuit technology

AU - Kiehl, R. A.

AU - Yates, J.

AU - Palmateer, L. F.

AU - Wright, S. L.

AU - Frank, D. J.

AU - Jackson, Thomas Nelson

AU - Degelormo, J. F.

AU - Fleischman, A. J.

PY - 1992/1/1

Y1 - 1992/1/1

N2 - A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.

AB - A III-V complementary heterostructure FET circuit technology which offers high-speed at low supply voltages has been demonstrated. This circuit technology is based on the vertical integration of p-channel quantum-well FETs with n-channel FETs fabricated in the underlying layers of a single-growth AlGaAs/GaAs structure. Key features of the p-FET heterostructure design and fabrication technology are discussed, and results on the electrical characteristics and the performance of high-speed ring oscillator circuits are presented. Delays of 144 and 59 ps are obtained in 0.8 and 0.5 μm gate-length circuits at a 1.25 V supply, which are the fastest speeds yet reported for room-temperature complementary heterostructure FET circuits at low supply voltages.

UR - http://www.scopus.com/inward/record.url?scp=0026743527&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026743527&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026743527

SN - 078030196X

T3 - Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

SP - 101

EP - 104

BT - Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

PB - Publ by IEEE

ER -

Kiehl RA, Yates J, Palmateer LF, Wright SL, Frank DJ, Jackson TN et al. High-speed, low-voltage complementary heterostructure FET circuit technology. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). Publ by IEEE. 1992. p. 101-104. (Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)).