Impact of circuit degradation on FPGA design security

Han Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages230-235
Number of pages6
DOIs
StatePublished - Sep 14 2011
Event2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India
Duration: Jul 4 2011Jul 6 2011

Publication series

NameProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Other

Other2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
CountryIndia
CityChennai
Period7/4/117/6/11

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chen, H. W., Srinivasan, S., Xie, Y., & Narayanan, V. (2011). Impact of circuit degradation on FPGA design security. In Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 (pp. 230-235). [5992485] (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011). https://doi.org/10.1109/ISVLSI.2011.81