Impact of contact and local interconnect scaling on logic performance

S. Datta, R. Pandey, A. Agrawal, S. K. Gupta, R. Arghavani

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Scopus citations

    Abstract

    We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.

    Original languageEnglish (US)
    Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781479933310
    DOIs
    StatePublished - Sep 8 2014
    Event34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States
    Duration: Jun 9 2014Jun 12 2014

    Publication series

    NameDigest of Technical Papers - Symposium on VLSI Technology
    ISSN (Print)0743-1562

    Other

    Other34th Symposium on VLSI Technology, VLSIT 2014
    CountryUnited States
    CityHonolulu
    Period6/9/146/12/14

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering

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