Impact of Dynamic Voltage Frequency Scaling on the Architectural Vulnerability of GALS architectures

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Aggressive technology scaling is increasing the impact of soft errors on microprocessor reliability. Dynamic Voltage Frequency Scaling (DFVS) algorithms are conventionally studied from a performance per watt basis. But applying DVFS impacts reliability as well. Since DVFS affects the occupancy of different pipeline structures, they impact the soft error masking seen at the architectural level. Architectural Vulnerability Factors (AVF) captures this masking and in this work we study the impact of DVFS on AVF in a GALS environment. We show that the AVF of pipeline structures could vary by as much as 80% between different DVFS algorithms. Since AVF has a significant impact on the Mean Time To Failure (MTTF) of a system, these results indicate that when choosing a particular DVFS algorithm their reliability impact cannot be ignored. Hence we provide the Vulnerability Efficiency for the DVFS algorithms which captures their ability to optimize performance, power and reliability. Our results show that a Non-DVFS environment optimizes vulnerability efficiency better than any of the DVFS algorithms.

Original languageEnglish (US)
Title of host publicationISLPED'08
Subtitle of host publicationProceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages351-356
Number of pages6
DOIs
StatePublished - Dec 17 2008
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: Aug 11 2008Aug 13 2008

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period8/11/088/13/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Soundararajan, N., Narayanan, V., & Sivasubramaniam, A. (2008). Impact of Dynamic Voltage Frequency Scaling on the Architectural Vulnerability of GALS architectures. In ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design (pp. 351-356). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1393921.1394016