Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS devices due to Negative Bias Temperature Instability (NBTI). NBTI has detrimental effects on the threshold voltage of the PMOS transistor thereby leading to lower performance and noise degradation over time in digital systems. The degradation is measured as reduction in Static Noise Margin (SNM) of SRAM cells in memories and as timing impact in digital circuits. In this work, we provide a comprehensive analysis of the impact of NBTI on different components for current and future generation FPGAs. We provide solutions based on the reversible nature of this phenomenon and the static probabilities at the gate of the PMOS devices in any system.We recover an average of 53.2% of the lost SNM and improve the FIT rate by 2.48% for a X4VFX40 device by using our proposed method.