Impact of NBTI on FPGAs

K. Ramakrishnan, S. Suresh, Vijaykrishnan Narayanan, Mary Jane Irwin, Vijay Degalahal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS devices due to Negative Bias Temperature Instability (NBTI). NBTI has detrimental effects on the threshold voltage of the PMOS transistor thereby leading to lower performance and noise degradation over time in digital systems. The degradation is measured as reduction in Static Noise Margin (SNM) of SRAM cells in memories and as timing impact in digital circuits. In this work, we provide a comprehensive analysis of the impact of NBTI on different components for current and future generation FPGAs. We provide solutions based on the reversible nature of this phenomenon and the static probabilities at the gate of the PMOS devices in any system.We recover an average of 53.2% of the lost SNM and improve the FIT rate by 2.48% for a X4VFX40 device by using our proposed method.

Original languageEnglish (US)
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages717-722
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: Jan 6 2007Jan 10 2007

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
CountryIndia
CityBangalore
Period1/6/071/10/07

Fingerprint

Field programmable gate arrays (FPGA)
Degradation
Static random access storage
Digital circuits
Threshold voltage
Transistors
Electric fields
Data storage equipment
Oxides
Negative bias temperature instability

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ramakrishnan, K., Suresh, S., Narayanan, V., Irwin, M. J., & Degalahal, V. (2007). Impact of NBTI on FPGAs. In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (pp. 717-722). [4092126] (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2007.91
Ramakrishnan, K. ; Suresh, S. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Degalahal, Vijay. / Impact of NBTI on FPGAs. Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. pp. 717-722 (Proceedings of the IEEE International Conference on VLSI Design).
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abstract = "Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS devices due to Negative Bias Temperature Instability (NBTI). NBTI has detrimental effects on the threshold voltage of the PMOS transistor thereby leading to lower performance and noise degradation over time in digital systems. The degradation is measured as reduction in Static Noise Margin (SNM) of SRAM cells in memories and as timing impact in digital circuits. In this work, we provide a comprehensive analysis of the impact of NBTI on different components for current and future generation FPGAs. We provide solutions based on the reversible nature of this phenomenon and the static probabilities at the gate of the PMOS devices in any system.We recover an average of 53.2{\%} of the lost SNM and improve the FIT rate by 2.48{\%} for a X4VFX40 device by using our proposed method.",
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Ramakrishnan, K, Suresh, S, Narayanan, V, Irwin, MJ & Degalahal, V 2007, Impact of NBTI on FPGAs. in Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems., 4092126, Proceedings of the IEEE International Conference on VLSI Design, pp. 717-722, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07, Bangalore, India, 1/6/07. https://doi.org/10.1109/VLSID.2007.91

Impact of NBTI on FPGAs. / Ramakrishnan, K.; Suresh, S.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Degalahal, Vijay.

Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. p. 717-722 4092126 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Ramakrishnan K, Suresh S, Narayanan V, Irwin MJ, Degalahal V. Impact of NBTI on FPGAs. In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. 2007. p. 717-722. 4092126. (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2007.91