Impact of Polysilicon Dry Etching on 0.5 µm NMOS Transistor Performance: The Presence of Both Plasma Bombardment Damage and Plasma Charging Damage

Tieer Gu, M. Okandan, O. O. Awadelkarim, S. J. Fonash, P. Aum, Y. D. Chan

Research output: Contribution to journalArticle

31 Scopus citations

Abstract

Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 µm NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging.

Original languageEnglish (US)
Pages (from-to)48-50
Number of pages3
JournalIEEE Electron Device Letters
Volume15
Issue number2
DOIs
StatePublished - Feb 1994

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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