Impact of process scaling on the efficacy of leakage reduction schemes

Yuh Fang Tsai, David Duarte, N. Vijaykrishnan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

Original languageEnglish (US)
Title of host publication2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages3-11
Number of pages9
StatePublished - Aug 30 2004
Event2004 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: May 17 2004May 20 2004

Publication series

Name2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other2004 International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period5/17/045/20/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Tsai, Y. F., Duarte, D., Vijaykrishnan, N., & Irwin, M. J. (2004). Impact of process scaling on the efficacy of leakage reduction schemes. In 2004 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 3-11). (2004 International Conference on Integrated Circuit Design and Technology, ICICDT).