Impact of process scaling on the efficacy of leakage reduction schemes

Yuh Fang Tsai, David Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

Original languageEnglish (US)
Title of host publication2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages3-11
Number of pages9
StatePublished - 2004
Event2004 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: May 17 2004May 20 2004

Other

Other2004 International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period5/17/045/20/04

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Data storage equipment

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Tsai, Y. F., Duarte, D., Narayanan, V., & Irwin, M. J. (2004). Impact of process scaling on the efficacy of leakage reduction schemes. In 2004 International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 3-11)
Tsai, Yuh Fang ; Duarte, David ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane. / Impact of process scaling on the efficacy of leakage reduction schemes. 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. pp. 3-11
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Tsai, YF, Duarte, D, Narayanan, V & Irwin, MJ 2004, Impact of process scaling on the efficacy of leakage reduction schemes. in 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. pp. 3-11, 2004 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, TX, United States, 5/17/04.

Impact of process scaling on the efficacy of leakage reduction schemes. / Tsai, Yuh Fang; Duarte, David; Narayanan, Vijaykrishnan; Irwin, Mary Jane.

2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. p. 3-11.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Narayanan, Vijaykrishnan

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AB - The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25um, 0.18 um, 0.07um and 0.065um technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.

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BT - 2004 International Conference on Integrated Circuit Design and Technology, ICICDT

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Tsai YF, Duarte D, Narayanan V, Irwin MJ. Impact of process scaling on the efficacy of leakage reduction schemes. In 2004 International Conference on Integrated Circuit Design and Technology, ICICDT. 2004. p. 3-11