Impact of process-variations in STTRAM and adaptive boosting for robustness

Seyedhamidreza Motaman, Swaroop Ghosh, Nitin Rathi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Citations (Scopus)

Abstract

Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10% due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80% power improvement compared to boosting all bit-cells and 13% performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1431-1436
Number of pages6
ISBN (Electronic)9783981537048
StatePublished - Apr 22 2015
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2015-April
ISSN (Print)1530-1591

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

Fingerprint

Adaptive boosting
Torque
Data storage equipment
Cache memory
Durability

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Motaman, S., Ghosh, S., & Rathi, N. (2015). Impact of process-variations in STTRAM and adaptive boosting for robustness. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (pp. 1431-1436). [7092615] (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April). Institute of Electrical and Electronics Engineers Inc..
Motaman, Seyedhamidreza ; Ghosh, Swaroop ; Rathi, Nitin. / Impact of process-variations in STTRAM and adaptive boosting for robustness. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1431-1436 (Proceedings -Design, Automation and Test in Europe, DATE).
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abstract = "Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10{\%} due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80{\%} power improvement compared to boosting all bit-cells and 13{\%} performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.",
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Motaman, S, Ghosh, S & Rathi, N 2015, Impact of process-variations in STTRAM and adaptive boosting for robustness. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015., 7092615, Proceedings -Design, Automation and Test in Europe, DATE, vol. 2015-April, Institute of Electrical and Electronics Engineers Inc., pp. 1431-1436, 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015, Grenoble, France, 3/9/15.

Impact of process-variations in STTRAM and adaptive boosting for robustness. / Motaman, Seyedhamidreza; Ghosh, Swaroop; Rathi, Nitin.

Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1431-1436 7092615 (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power. Additionally, it offers fast access time, good endurance and retention. However, it suffers from poor write latency and write power. Additionally we observe that process variation can result in large spread in write and read latency variations. The performance of conventionally designed STTRAM cache can degrade as much as 10% due to process variations. We propose a novel and adaptive write current boosting to address this issue. The bits experiencing worst-case write latency are fixed through write current boosting. Simulations show 80% power improvement compared to boosting all bit-cells and 13% performance improvement compared to worst case latency due to process variation over a wide range of PARSEC benchmarks.

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Motaman S, Ghosh S, Rathi N. Impact of process-variations in STTRAM and adaptive boosting for robustness. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1431-1436. 7092615. (Proceedings -Design, Automation and Test in Europe, DATE).