Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures

S. Eachempati, N. Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alternative interconnect solutions for future process technologies. In this paper, we investigate the impact of statistical variations in interconnect properties on FPGA timing yield (TY) when bundles of single-walled carbon nanotubes (SWCNT) are used as interconnect in the FPGA routing fabric. The results indicate that SWCNT bundle-based interconnect (SWCNTBI) can provide a superior performance-yield trade-off over FPGAs implemented using traditional CuI in future process technologies.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging VLSI Technologies and Architectures
Pages516-517
Number of pages2
DOIs
StatePublished - Nov 28 2007
EventIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil
Duration: Mar 9 2007Mar 11 2007

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Other

OtherIEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
CountryBrazil
CityPorto Alegre
Period3/9/073/11/07

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Eachempati, S., Vijaykrishnan, N., Nieuwoudt, A., & Massoud, Y. (2007). Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (pp. 516-517). [4208978] (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). https://doi.org/10.1109/ISVLSI.2007.56