Impact of technology scaling and packaging on dynamic voltage scaling techniques

D. Duarte; Vijaykrishnan Narayanan; Mary Jane Irwin; Y. F. Tsai

doi:10.1109/ASIC.2002.1158064

Impact of technology scaling and packaging on dynamic voltage scaling techniques

D. Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin, Y. F. Tsai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that V_dd scaling maintains its effectiveness while V_th scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.

Original language	English (US)
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	244-248
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158064
State	Published - Jan 1 2002
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country	United States
City	Rochester
Period	9/25/02 → 9/28/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158064

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Duarte, D., Narayanan, V., Irwin, M. J., & Tsai, Y. F. (2002). Impact of technology scaling and packaging on dynamic voltage scaling techniques. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 244-248). [1158064] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158064

Duarte, D. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Tsai, Y. F. / Impact of technology scaling and packaging on dynamic voltage scaling techniques. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 244-248 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

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abstract = "This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.",

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Duarte, D, Narayanan, V, Irwin, MJ & Tsai, YF 2002, Impact of technology scaling and packaging on dynamic voltage scaling techniques. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158064, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 244-248, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158064

Impact of technology scaling and packaging on dynamic voltage scaling techniques. / Duarte, D.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Tsai, Y. F.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 244-248 1158064 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.

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Duarte D, Narayanan V, Irwin MJ, Tsai YF. Impact of technology scaling and packaging on dynamic voltage scaling techniques. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 244-248. 1158064. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). https://doi.org/10.1109/ASIC.2002.1158064