@inproceedings{d28b2af986734b2baac34815cac40fbc,
title = "Impact of technology scaling and packaging on dynamic voltage scaling techniques",
abstract = "This paper studies how the effectiveness of various Dynamic Voltage Scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.",
author = "D. Duarte and Vijaykrishnan Narayanan and Irwin, {Mary Jane} and Tsai, {Y. F.}",
year = "2002",
month = jan,
day = "1",
doi = "10.1109/ASIC.2002.1158064",
language = "English (US)",
series = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "244--248",
editor = "John Chickanosky and Krishnamurthy, {Ram K.} and P.R. Mukund",
booktitle = "Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002",
address = "United States",
note = "15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 ; Conference date: 25-09-2002 Through 28-09-2002",
}