Impact of technology scaling in the clock system power

D. Duarte, V. Narayanan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Scopus citations

Abstract

The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed while a comprehensive framework for the estimation of systemwide (chip level) and clock sub-system power as function of technology scaling is presented. This framework is used to study and quantify the impact that various intensifying concerns associated with scaling (i.e., increased leakage currents, increased interwire capacitance) will have on clock energy and their relative impact on the overall system energy. The results obtained indicate that clock power will remain a significant contributor to the total chip power, as long as techniques are used to limit leakage power consumption.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationNew Paradigms for VLSI Systems Design, ISVLSI 2002
EditorsAsim Smailagic, Robert Brodersen
PublisherIEEE Computer Society
Pages59-64
Number of pages6
ISBN (Electronic)0769514863
DOIs
StatePublished - 2002
EventIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 - Pittsburgh, United States
Duration: Apr 25 2002Apr 26 2002

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2002-January
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Other

OtherIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002
CountryUnited States
CityPittsburgh
Period4/25/024/26/02

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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