Implementing a family of high performance, micrograined architectures

Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder S. Bajwa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper describes the design and implementation of high performance micro-grained architectures. These architectures are capable of teraops performance. Each architecture is organized as a systolic array of processors. A prototyping system for the architectures is proposed. The prototyping system will provide control, I/O, and an interface to a host system for each of the micro-grained architectures. The prototyping system has been designed with flexibility in mind to support a wide variety of these micro-grained architectures. Beyond the research outlined here, we anticipate using the prototyping system as a `test-bed' for various class/student VLSI design projects within the department. Three micro-grained architectures are described: an associative memory-based architecture, a Mux-based architecture and a RAM-based architecture. These architectures will be useful for solving a number of important problems, such as: edge detection, locating connected components, two-dimensional signal and image processing, sorting elements, and performing element permutations.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Application
PublisherPubl by IEEE
Pages191-205
Number of pages15
ISBN (Print)0818629673
StatePublished - Dec 1 1992
EventProceedings of the International Conference on Application Specific Array Processors - Berkeley, CA, USA
Duration: Aug 4 1992Aug 7 1992

Publication series

NameProceedings of the International Conference on Application

Other

OtherProceedings of the International Conference on Application Specific Array Processors
CityBerkeley, CA, USA
Period8/4/928/7/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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