Implementing LDPC decoding on network-on-chip

T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to their ability to achieve near Shannon-limit communication channel capacity, the computational complexity of the decoder is a major concern. LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph. In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip communication fabric that provides a 1.2Gbps decoded throughput rate for a 3/4 code rate, 1024-bit block LDPC code. The proposed architecture can be reconfigured to support other LDPC codes of different block sizes and code rates. We also propose two novel power-aware optimizations that reduce the power consumption by up to 30%.

Original languageEnglish (US)
Title of host publicationProceedings of the 18th International Conference on VLSI Design
Pages134-137
Number of pages4
DOIs
StatePublished - 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other18th International Conference on VLSI Design: Power Aware Design of VLSI Systems
Country/TerritoryIndia
CityKolkata
Period1/3/051/7/05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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