Improving bank-level parallelism for irregular applications

Xulong Tang, Mahmut Kandemir, Praveen Yedlapalli, Jagadish Kotra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

Observing that large multithreaded applications with irregular data access patterns exhibit very low memory bank-level parallelism (BLP) during their execution, we propose a novel loop iteration scheduling strategy built upon the inspector-executor paradigm. A unique characteristic of this strategy is that it considers both bank-level parallelism (from an inter-core perspective) and bank reuse (from an intra-core perspective) in a unified framework. Its primary goal is to improve bank-level parallelism, and bank reuse is taken into account only if doing so does not hurt bank-level parallelism. Our experiments with this strategy using eight application programs on both a simulator and a real multicore system show an average BLP improvement of 46.8% and an average execution time reduction of 18.3%.

Original languageEnglish (US)
Title of host publicationMICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture
PublisherIEEE Computer Society
ISBN (Electronic)9781509035083
DOIs
StatePublished - Dec 14 2016
Event49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016 - Taipei, Taiwan, Province of China
Duration: Oct 15 2016Oct 19 2016

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2016-December
ISSN (Print)1072-4451

Other

Other49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016
CountryTaiwan, Province of China
CityTaipei
Period10/15/1610/19/16

Fingerprint

Application programs
Simulators
Scheduling
Data storage equipment
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Tang, X., Kandemir, M., Yedlapalli, P., & Kotra, J. (2016). Improving bank-level parallelism for irregular applications. In MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture [7783760] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; Vol. 2016-December). IEEE Computer Society. https://doi.org/10.1109/MICRO.2016.7783760
Tang, Xulong ; Kandemir, Mahmut ; Yedlapalli, Praveen ; Kotra, Jagadish. / Improving bank-level parallelism for irregular applications. MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2016. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).
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Tang, X, Kandemir, M, Yedlapalli, P & Kotra, J 2016, Improving bank-level parallelism for irregular applications. in MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture., 7783760, Proceedings of the Annual International Symposium on Microarchitecture, MICRO, vol. 2016-December, IEEE Computer Society, 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, Province of China, 10/15/16. https://doi.org/10.1109/MICRO.2016.7783760

Improving bank-level parallelism for irregular applications. / Tang, Xulong; Kandemir, Mahmut; Yedlapalli, Praveen; Kotra, Jagadish.

MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2016. 7783760 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; Vol. 2016-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Tang X, Kandemir M, Yedlapalli P, Kotra J. Improving bank-level parallelism for irregular applications. In MICRO 2016 - 49th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society. 2016. 7783760. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2016.7783760