Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via

Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei Hao Chen, Kuo Hsinag Hsu, Xueqing Li, Meng Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories on the upper stack. Along with the reconfigurability feature, results show that our SLICE design offers an area reduction of 23% compared to a standard design without reconfiguration capability. Our analysis of FPGA switch box logic and physical design with M3D vias provides insights into the sources of benefits from vertical routing in a multi-stacked design. We also discuss the design overheads involved in incorporating multiple inter-stack vias for better and faster communication among logic routed in different design stacks.

Original languageEnglish (US)
Title of host publicationProceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
EditorsRicardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
PublisherIEEE Computer Society
Pages128-133
Number of pages6
ISBN (Electronic)9781509067626
DOIs
StatePublished - Jul 20 2017
Event2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany
Duration: Jul 3 2017Jul 5 2017

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2017-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Other

Other2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
CountryGermany
CityBochum, North Rhine-Westfalia
Period7/3/177/5/17

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Srinivasa, S. R., Mohan, K., Chen, W. H., Hsu, K. H., Li, X., Chang, M. F., Gupta, S. K., Sampson, J., & Narayanan, V. (2017). Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 128-133). [7987507] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.31