Improving ILP with instruction-reuse cache hierarchy

D. Charles, A. R. Hurson, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Instruction reuse is an interesting strategy for improving processor performance. Several techniques at fine and coarse granularities have been proposed to extend instruction reuse. Among them block and trace reuse are the most promising. This work studies the benefits of combining block and trace reuse with instruction reuse to form an instruction reuse cache hierarchy. A simple reuse hierarchy is implemented and tested with select SPEC95 benchmarks. Both instruction reuse and ILP show modest performance improvements when compared to the base schemes. Within the scope of the selected benchmarks, the proposed reuse policy reuses as much as 60% of possible reusable instructions and shows an average ILP gain of 13.83%. This paper introduces the proposed reuse model and its simulation. The simulation results are presented and analyzed. Finally, future research directions in this area have been discussed.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002
EditorsWanlei Zhou, Andrzej Goscinski, Guo-jie Li, Xue-bin Chi
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages206-213
Number of pages8
ISBN (Electronic)0769515126, 9780769515120
DOIs
StatePublished - Jan 1 2002
Event5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002 - Beijing, China
Duration: Oct 23 2002Oct 25 2002

Publication series

NameProceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002

Other

Other5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002
CountryChina
CityBeijing
Period10/23/0210/25/02

Fingerprint

Inductive logic programming (ILP)
Cache
Reuse
Hierarchy
Trace
Benchmark
Granularity
Simulation

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Mathematics(all)

Cite this

Charles, D., Hurson, A. R., & Narayanan, V. (2002). Improving ILP with instruction-reuse cache hierarchy. In W. Zhou, A. Goscinski, G. Li, & X. Chi (Eds.), Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002 (pp. 206-213). [1173575] (Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAPP.2002.1173575
Charles, D. ; Hurson, A. R. ; Narayanan, Vijaykrishnan. / Improving ILP with instruction-reuse cache hierarchy. Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002. editor / Wanlei Zhou ; Andrzej Goscinski ; Guo-jie Li ; Xue-bin Chi. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 206-213 (Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002).
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Charles, D, Hurson, AR & Narayanan, V 2002, Improving ILP with instruction-reuse cache hierarchy. in W Zhou, A Goscinski, G Li & X Chi (eds), Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002., 1173575, Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002, Institute of Electrical and Electronics Engineers Inc., pp. 206-213, 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002, Beijing, China, 10/23/02. https://doi.org/10.1109/ICAPP.2002.1173575

Improving ILP with instruction-reuse cache hierarchy. / Charles, D.; Hurson, A. R.; Narayanan, Vijaykrishnan.

Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002. ed. / Wanlei Zhou; Andrzej Goscinski; Guo-jie Li; Xue-bin Chi. Institute of Electrical and Electronics Engineers Inc., 2002. p. 206-213 1173575 (Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Instruction reuse is an interesting strategy for improving processor performance. Several techniques at fine and coarse granularities have been proposed to extend instruction reuse. Among them block and trace reuse are the most promising. This work studies the benefits of combining block and trace reuse with instruction reuse to form an instruction reuse cache hierarchy. A simple reuse hierarchy is implemented and tested with select SPEC95 benchmarks. Both instruction reuse and ILP show modest performance improvements when compared to the base schemes. Within the scope of the selected benchmarks, the proposed reuse policy reuses as much as 60% of possible reusable instructions and shows an average ILP gain of 13.83%. This paper introduces the proposed reuse model and its simulation. The simulation results are presented and analyzed. Finally, future research directions in this area have been discussed.

AB - Instruction reuse is an interesting strategy for improving processor performance. Several techniques at fine and coarse granularities have been proposed to extend instruction reuse. Among them block and trace reuse are the most promising. This work studies the benefits of combining block and trace reuse with instruction reuse to form an instruction reuse cache hierarchy. A simple reuse hierarchy is implemented and tested with select SPEC95 benchmarks. Both instruction reuse and ILP show modest performance improvements when compared to the base schemes. Within the scope of the selected benchmarks, the proposed reuse policy reuses as much as 60% of possible reusable instructions and shows an average ILP gain of 13.83%. This paper introduces the proposed reuse model and its simulation. The simulation results are presented and analyzed. Finally, future research directions in this area have been discussed.

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Charles D, Hurson AR, Narayanan V. Improving ILP with instruction-reuse cache hierarchy. In Zhou W, Goscinski A, Li G, Chi X, editors, Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 206-213. 1173575. (Proceedings - 5th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2002). https://doi.org/10.1109/ICAPP.2002.1173575