Improving Java performance using dynamic method migration on FPGAs

Emanuele Lattanzi, Aman Gayasen, Mahmut Kandemir, Vijaykrishnan Narayanan, Luca Benini, Alessandro Bogliolo

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialised execution engine on speed-critical bytecode. This work proposes and analyses a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyse speedups achievable under a number of system configurations using an accurate complete-system simulator.

Original languageEnglish (US)
Pages (from-to)228-236
Number of pages9
JournalInternational Journal of Embedded Systems
Volume1
Issue number3-4
StatePublished - Jan 1 2005

Fingerprint

Field programmable gate arrays (FPGA)
Microprocessor chips
Mobile devices
Simulators
Engines
Data storage equipment
Communication
Coprocessor

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

Lattanzi, Emanuele ; Gayasen, Aman ; Kandemir, Mahmut ; Narayanan, Vijaykrishnan ; Benini, Luca ; Bogliolo, Alessandro. / Improving Java performance using dynamic method migration on FPGAs. In: International Journal of Embedded Systems. 2005 ; Vol. 1, No. 3-4. pp. 228-236.
@article{6d976c4891ac41c99dedf57312891340,
title = "Improving Java performance using dynamic method migration on FPGAs",
abstract = "With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialised execution engine on speed-critical bytecode. This work proposes and analyses a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyse speedups achievable under a number of system configurations using an accurate complete-system simulator.",
author = "Emanuele Lattanzi and Aman Gayasen and Mahmut Kandemir and Vijaykrishnan Narayanan and Luca Benini and Alessandro Bogliolo",
year = "2005",
month = "1",
day = "1",
language = "English (US)",
volume = "1",
pages = "228--236",
journal = "International Journal of Embedded Systems",
issn = "1741-1068",
publisher = "Inderscience Enterprises Ltd",
number = "3-4",

}

Lattanzi, E, Gayasen, A, Kandemir, M, Narayanan, V, Benini, L & Bogliolo, A 2005, 'Improving Java performance using dynamic method migration on FPGAs', International Journal of Embedded Systems, vol. 1, no. 3-4, pp. 228-236.

Improving Java performance using dynamic method migration on FPGAs. / Lattanzi, Emanuele; Gayasen, Aman; Kandemir, Mahmut; Narayanan, Vijaykrishnan; Benini, Luca; Bogliolo, Alessandro.

In: International Journal of Embedded Systems, Vol. 1, No. 3-4, 01.01.2005, p. 228-236.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Improving Java performance using dynamic method migration on FPGAs

AU - Lattanzi, Emanuele

AU - Gayasen, Aman

AU - Kandemir, Mahmut

AU - Narayanan, Vijaykrishnan

AU - Benini, Luca

AU - Bogliolo, Alessandro

PY - 2005/1/1

Y1 - 2005/1/1

N2 - With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialised execution engine on speed-critical bytecode. This work proposes and analyses a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyse speedups achievable under a number of system configurations using an accurate complete-system simulator.

AB - With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialised execution engine on speed-critical bytecode. This work proposes and analyses a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyse speedups achievable under a number of system configurations using an accurate complete-system simulator.

UR - http://www.scopus.com/inward/record.url?scp=70349140776&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70349140776&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:70349140776

VL - 1

SP - 228

EP - 236

JO - International Journal of Embedded Systems

JF - International Journal of Embedded Systems

SN - 1741-1068

IS - 3-4

ER -