Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

Kaisheng Ma, Huichu Liu, Yang Xiao, Yang Zheng, Xueqing Li, Sumeet Kumar Gupta, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

In this paper, two novel 6T SRAM cells based on Independently-Controlled-Gate FinFETs are proposed. The new 6T cells are derived from 4T cells: by separating the read timing and read-line, the proposed new cells allow simultaneously read & write to different addresses. To overcome the traditional retention time problem in 4T cells, the proposed cells reduce leakage by changing the back-gate connection and increasing the capacitance at data storage points (Q, QB). Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed. In addition, this structure is scalable for multi-ports.

Original languageEnglish (US)
Title of host publicationProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
PublisherIEEE Computer Society
Pages296-301
Number of pages6
ISBN (Electronic)9781479937639
DOIs
StatePublished - Sep 18 2014
Event2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States
Duration: Jul 9 2014Jul 11 2014

Other

Other2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
CountryUnited States
CityTampa
Period7/9/147/11/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Ma, K., Liu, H., Xiao, Y., Zheng, Y., Li, X., Gupta, S. K., Xie, Y., & Narayanan, V. (2014). Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI (pp. 296-301). [6903379] IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2014.25