Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs

Arun V. Thathachary, N. Agrawal, K. K. Bhuwalka, M. Cantoro, Y. C. Heo, Guy Lavallee, S. Maeda, S. Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

This work presents experimental demonstration of InAs single and dual quantum well (DQW) heterostructure FinFETs (FF) and their superior performance over In0.7Ga0.3As QW FF. Peak mobility of 3,531 cm2/V-sec and 3,950 cm2/V-sec are obtained for InAs single QW FF and InAs DQW FF, respectively, at a fin width (Wfin) of 40nm and LG = 2μm. Peak gm of 480 μS/μm, 541 μS/um; IDSAT of 121 μA/μm, 135 μA/μm; and SSSAT of 101 mV/dec,103 mV/dec is demonstrated for single and DQW FF, respectively, at LG=300nm (VD = 0.5V, IOFF=100 nA/μm). Finally, InAs DQW is shown to be a viable alternate channel for high aspect ratio n-channel FinFET.

Original languageEnglish (US)
Title of host publication2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT208-T209
ISBN (Electronic)9784863485013
DOIs
StatePublished - Aug 25 2015
EventSymposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan
Duration: Jun 16 2015Jun 18 2015

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2015-August
ISSN (Print)0743-1562

Other

OtherSymposium on VLSI Technology, VLSI Technology 2015
CountryJapan
CityKyoto
Period6/16/156/18/15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Thathachary, A. V., Agrawal, N., Bhuwalka, K. K., Cantoro, M., Heo, Y. C., Lavallee, G., Maeda, S., & Datta, S. (2015). Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs. In 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (pp. T208-T209). [7223677] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223677