Influence of communication optimizations on on-chip multi-processor energy

I. Kadayif, Mahmut Kandemir, G. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Designing cost-effective and scalable on-chip multi-processors demand careful attention be paid to software. In particular, if not optimized, the energy consumption due to interprocessor communication can be overwhelming. In this paper, we focus on array-intensive applications and study the energy impact of inter-processor communication optimizations on a private memory based on-chip multi-processor. Our results emphasize the importance of considering both computation energy and communication energy when applying optimizations that reduce inter-processor communication.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2003
EditorsDong S. Ha, Richard Auletta, John Chickanosky
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages255-256
Number of pages2
ISBN (Electronic)0780381823, 9780780381827
DOIs
StatePublished - Jan 1 2003
EventIEEE International SOC Conference, SOCC 2003 - Portland, United States
Duration: Sep 17 2003Sep 20 2003

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2003

Other

OtherIEEE International SOC Conference, SOCC 2003
CountryUnited States
CityPortland
Period9/17/039/20/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Kadayif, I., Kandemir, M., & Chen, G. (2003). Influence of communication optimizations on on-chip multi-processor energy. In D. S. Ha, R. Auletta, & J. Chickanosky (Eds.), Proceedings - IEEE International SOC Conference, SOCC 2003 (pp. 255-256). [1241508] (Proceedings - IEEE International SOC Conference, SOCC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOC.2003.1241508