Influence of leakage reduction techniques on delay/leakage uncertainty

Yuh Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin

Research output: Contribution to journalConference article

17 Citations (Scopus)

Abstract

One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V dd/V th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.

Original languageEnglish (US)
Pages (from-to)374-379
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - Dec 1 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

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Uncertainty
Temperature

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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Influence of leakage reduction techniques on delay/leakage uncertainty. / Tsai, Yuh Fang; Narayanan, Vijaykrishnan; Xie, Yuan; Irwin, Mary Jane.

In: Proceedings of the IEEE International Conference on VLSI Design, 01.12.2005, p. 374-379.

Research output: Contribution to journalConference article

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AU - Narayanan, Vijaykrishnan

AU - Xie, Yuan

AU - Irwin, Mary Jane

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