Input sensitive high-level power analysis

J. Hezavei, Vijaykrishnan Narayanan, Mary Jane Irwin, Mahmut Kandemir, D. Duarte

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.

Original languageEnglish (US)
Pages (from-to)149-156
Number of pages8
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
DOIs
StatePublished - Jan 1 2001

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Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Signal Processing

Cite this

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Input sensitive high-level power analysis. / Hezavei, J.; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Kandemir, Mahmut; Duarte, D.

In: IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 01.01.2001, p. 149-156.

Research output: Contribution to journalArticle

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