Input sensitive high-level power analysis

J. Hezavei, N. Vijaykrishnan, M. J. Irwin, M. Kandemir, D. Duarte

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.

Original languageEnglish (US)
Pages (from-to)149-156
Number of pages8
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
DOIs
StatePublished - Jan 1 2001

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Signal Processing

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