In this paper, an input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25um, 2.5V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.
|Original language||English (US)|
|Number of pages||8|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - Jan 1 2001|
All Science Journal Classification (ASJC) codes
- Media Technology
- Signal Processing