Abstract
Low-power system design is very important in battery-operated embedded systems. Since instruction memory constitutes a large portion of the system, it is one of the major energy contributors. In this paper, we propose two selective instruction compression methods for reducing instruction memory and instruction bus energy consumption. In these methods, both compressed and uncompressed instructions are stored in the instruction memory in a mixed fashion. The compressed instructions are decompressed on-the-fly by means of an instruction decode table placed between instruction memory and core. Our methods selectively compress instructions in the sense that while some instances of a given instruction are compressed, some other instances of the same instruction are not. Even though both of the proposed methods can reduce both dynamic and leakage energy consumption in the instruction memory, one of them is more oriented towards reducing dynamic energy, whereas the other one mainly targets leakage. To reduce the instruction bus energy consumption further, we also propose a heuristic method for coding compressed instructions to reduce bit switching on the bus.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 301-305 |
| Number of pages | 5 |
| Volume | 2002-January |
| ISBN (Electronic) | 0780374940 |
| DOIs | |
| State | Published - 2002 |
| Event | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002 |
Other
| Other | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
|---|---|
| Country | United States |
| City | Rochester |
| Period | 9/25/02 → 9/28/02 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Instruction compression and encoding for low-power systems. / Kadayif, Ismail; Kandemir, Mahmut.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 301-305 1158075.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Instruction compression and encoding for low-power systems
AU - Kadayif, Ismail
AU - Kandemir, Mahmut
PY - 2002
Y1 - 2002
N2 - Low-power system design is very important in battery-operated embedded systems. Since instruction memory constitutes a large portion of the system, it is one of the major energy contributors. In this paper, we propose two selective instruction compression methods for reducing instruction memory and instruction bus energy consumption. In these methods, both compressed and uncompressed instructions are stored in the instruction memory in a mixed fashion. The compressed instructions are decompressed on-the-fly by means of an instruction decode table placed between instruction memory and core. Our methods selectively compress instructions in the sense that while some instances of a given instruction are compressed, some other instances of the same instruction are not. Even though both of the proposed methods can reduce both dynamic and leakage energy consumption in the instruction memory, one of them is more oriented towards reducing dynamic energy, whereas the other one mainly targets leakage. To reduce the instruction bus energy consumption further, we also propose a heuristic method for coding compressed instructions to reduce bit switching on the bus.
AB - Low-power system design is very important in battery-operated embedded systems. Since instruction memory constitutes a large portion of the system, it is one of the major energy contributors. In this paper, we propose two selective instruction compression methods for reducing instruction memory and instruction bus energy consumption. In these methods, both compressed and uncompressed instructions are stored in the instruction memory in a mixed fashion. The compressed instructions are decompressed on-the-fly by means of an instruction decode table placed between instruction memory and core. Our methods selectively compress instructions in the sense that while some instances of a given instruction are compressed, some other instances of the same instruction are not. Even though both of the proposed methods can reduce both dynamic and leakage energy consumption in the instruction memory, one of them is more oriented towards reducing dynamic energy, whereas the other one mainly targets leakage. To reduce the instruction bus energy consumption further, we also propose a heuristic method for coding compressed instructions to reduce bit switching on the bus.
UR - http://www.scopus.com/inward/record.url?scp=24944432943&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=24944432943&partnerID=8YFLogxK
U2 - 10.1109/ASIC.2002.1158075
DO - 10.1109/ASIC.2002.1158075
M3 - Conference contribution
VL - 2002-January
SP - 301
EP - 305
BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
PB - Institute of Electrical and Electronics Engineers Inc.
ER -