Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost

Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8x8 Wallace tree multiplier in 90nm technology node show 20% reduction in operating power, 60% reduction in test power and 99% reduction in critical paths while at the same time improving the yield from 96% to 100%, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8%).

Original languageEnglish (US)
Title of host publicationProceedings of the 20th Asian Test Symposium, ATS 2011
Number of pages6
StatePublished - Dec 1 2011
Event20th Asian Test Symposium, ATS 2011 - New Delhi, India
Duration: Nov 20 2011Nov 23 2011

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other20th Asian Test Symposium, ATS 2011
CityNew Delhi

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost'. Together they form a unique fingerprint.

Cite this