Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost

Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8x8 Wallace tree multiplier in 90nm technology node show 20% reduction in operating power, 60% reduction in test power and 99% reduction in critical paths while at the same time improving the yield from 96% to 100%, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8%).

Original languageEnglish (US)
Title of host publicationProceedings of the 20th Asian Test Symposium, ATS 2011
Pages486-491
Number of pages6
DOIs
StatePublished - Dec 1 2011
Event20th Asian Test Symposium, ATS 2011 - New Delhi, India
Duration: Nov 20 2011Nov 23 2011

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other20th Asian Test Symposium, ATS 2011
CountryIndia
CityNew Delhi
Period11/20/1111/23/11

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Goel, A., Ghosh, S., Meterelliyoz, M., Parkhurst, J., & Roy, K. (2011). Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost. In Proceedings of the 20th Asian Test Symposium, ATS 2011 (pp. 486-491). [6114721] (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2011.100
Goel, Ashish ; Ghosh, Swaroop ; Meterelliyoz, Mesut ; Parkhurst, Jeff ; Roy, Kaushik. / Integrated design & test : Conquering the conflicting requirements of low-power, variation-tolerance and test cost. Proceedings of the 20th Asian Test Symposium, ATS 2011. 2011. pp. 486-491 (Proceedings of the Asian Test Symposium).
@inproceedings{2e2df27b5a484de38009eb40b4656553,
title = "Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost",
abstract = "Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8x8 Wallace tree multiplier in 90nm technology node show 20{\%} reduction in operating power, 60{\%} reduction in test power and 99{\%} reduction in critical paths while at the same time improving the yield from 96{\%} to 100{\%}, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8{\%}).",
author = "Ashish Goel and Swaroop Ghosh and Mesut Meterelliyoz and Jeff Parkhurst and Kaushik Roy",
year = "2011",
month = "12",
day = "1",
doi = "10.1109/ATS.2011.100",
language = "English (US)",
isbn = "9780769545837",
series = "Proceedings of the Asian Test Symposium",
pages = "486--491",
booktitle = "Proceedings of the 20th Asian Test Symposium, ATS 2011",

}

Goel, A, Ghosh, S, Meterelliyoz, M, Parkhurst, J & Roy, K 2011, Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost. in Proceedings of the 20th Asian Test Symposium, ATS 2011., 6114721, Proceedings of the Asian Test Symposium, pp. 486-491, 20th Asian Test Symposium, ATS 2011, New Delhi, India, 11/20/11. https://doi.org/10.1109/ATS.2011.100

Integrated design & test : Conquering the conflicting requirements of low-power, variation-tolerance and test cost. / Goel, Ashish; Ghosh, Swaroop; Meterelliyoz, Mesut; Parkhurst, Jeff; Roy, Kaushik.

Proceedings of the 20th Asian Test Symposium, ATS 2011. 2011. p. 486-491 6114721 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Integrated design & test

T2 - Conquering the conflicting requirements of low-power, variation-tolerance and test cost

AU - Goel, Ashish

AU - Ghosh, Swaroop

AU - Meterelliyoz, Mesut

AU - Parkhurst, Jeff

AU - Roy, Kaushik

PY - 2011/12/1

Y1 - 2011/12/1

N2 - Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8x8 Wallace tree multiplier in 90nm technology node show 20% reduction in operating power, 60% reduction in test power and 99% reduction in critical paths while at the same time improving the yield from 96% to 100%, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8%).

AB - Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8x8 Wallace tree multiplier in 90nm technology node show 20% reduction in operating power, 60% reduction in test power and 99% reduction in critical paths while at the same time improving the yield from 96% to 100%, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8%).

UR - http://www.scopus.com/inward/record.url?scp=84856149949&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84856149949&partnerID=8YFLogxK

U2 - 10.1109/ATS.2011.100

DO - 10.1109/ATS.2011.100

M3 - Conference contribution

AN - SCOPUS:84856149949

SN - 9780769545837

T3 - Proceedings of the Asian Test Symposium

SP - 486

EP - 491

BT - Proceedings of the 20th Asian Test Symposium, ATS 2011

ER -

Goel A, Ghosh S, Meterelliyoz M, Parkhurst J, Roy K. Integrated design & test: Conquering the conflicting requirements of low-power, variation-tolerance and test cost. In Proceedings of the 20th Asian Test Symposium, ATS 2011. 2011. p. 486-491. 6114721. (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2011.100