Interconnect and thermal-aware floorplanning for 3D microprocessors

W. L. Hung, G. M. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

148 Scopus citations

Abstract

Interconnects are becoming an increasing problem from both performance and power consumption perspective in future technology nodes. The introduction of 3D chip architectures, with their intrinsic capability of reducing wire length, is one of the promising solutions to mitigate the interconnect problem. While interconnect power consumption reduces due to the adoption of 3D designs, the stacking of multiple active layers leads to higher power densities. Thus, high peak temperatures are of major concern in 3D designs. Consequently, we present a thermal-aware floorplanner for 3D architectures. In contrast to most prior work, our floorplanner considers the interconnect power consumption in exploring a thermal-aware floorplan. Our results show that excluding interconnect power can result in peak temperatures being underestimated by as much as 15/spl deg/C in 90nm technology. Finally, we demonstrate that our floorplanner is effective in lowering peak temperatures using a microprocessor design and four MCNC designs as benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Pages98-104
Number of pages7
DOIs
StatePublished - Dec 1 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: Mar 27 2006Mar 29 2006

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period3/27/063/29/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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    Hung, W. L., Link, G. M., Xie, Y., Vijaykrishnan, N., & Irwin, M. J. (2006). Interconnect and thermal-aware floorplanning for 3D microprocessors. In Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006 (pp. 98-104). [1613120] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2006.77